In most complex electronic systems, data is transferred between clock domains that operate at various clock frequencies. When data is transferred across a clock boundary from a clock domain with one clock frequency to a clock domain with a different clock frequency, some synchronization mechanism is typically employed. The synchronization mechanism assures, for example, that circuitry in the receiving clock domain samples transmitted data when it is valid. The synchronization mechanism accounts for differences in clock frequency, and possibly delays caused by physical path characteristics, to assure proper setup and hold times for digital data signals.
FIG. 1 is a block diagram showing portions of a prior art system 100. The system 100 includes a system input/output (“I/O”) component 102, a clock source 104, and a dependent clock generator 106. The system I/O component 102 encompasses two clock domains, clock domain A and clock domain B separated by a clock domain boundary 108. The system component 102 is an example of a component that receives and transmits data across one or more clock domain boundaries. For example, the system component 102 may be a semiconductor chip or “chipset” that performs multiple data I/O functions, such as a memory controller function and a memory interface function. As an example, part of the functionality of the clock domain A is a memory controller 110, and part of the functionality of the clock domain B is a memory interface 112. Many memory components operate at high speeds relative to other system components. Most system components communicate with memory components. Therefore, the memory controller 110 of clock domain A receives data from and transmits data to memory components for a variety of system components, such as front-side buses, processors, graphics controllers, etc. The memory controller 110 includes gear ratio logic 114 and data and control logic 116. The memory controller components operate at the rate of a PCLK clock signal, which is supplied by the clock source 104.
The memory interface 112 includes a divide-by-X circuit 118 and data and control logic 120. The components of the memory interface 112 operate at the rate of a CLKIN clock signal. CLKIN is faster than PCLK and is generated by the dependent clock generator 106. Typically, the rate of CLKIN is a multiple of the rate of PCLK. In one direction of transmission, the data bits D0-D3 on the data lines 122 are received by the data and control logic 116 and placed on the parallel data lines D0-D3 each cycle of PCLK. Data and control logic 120 is capable of receiving the four bits of data in parallel and placing them on the serial data line 124 each cycle of CLKIN. The data and control logic 120 must sample the data on the data lines D0-D3 at the appropriate times in order to assure that the data is valid and to maximize throughput. In order to assure accurate data transmission and sampling across the timing boundary 108, the two clocks operating data and control logic 116 and data and control logic 120 must be kept in phase alignment. In addition, because there may be multiple edges of the faster clock available for sampling data in a given cycle of the slower clock, there must be a mechanism for determining which edges of the faster clock to use for sampling data.
The gear ratio logic 114 is used to generate two signals, PCLK/M and SCLK/N, each having a common frequency for phase alignment. The values of M and N are chosen based on the frequencies of PCLK and SCLK so that the resulting PCLK/M and SCLK/N have a common frequency. SCLK/N and PCLK/M are transmitted to phase detector and phase alignment circuitry in the dependent clock generator 106. In this way, the clocks from each of the clock domains A and B can be phase aligned so that data is sampled accurately across the timing boundary 108. The phase alignment process of system 100, as explained above, has disadvantages. For example, M/N is usually not the true ratio relationship between PCLK and CLKIN because, in the system of FIG. 1, CLKIN is first divided by X in the fixed divide-by-X circuit 118. This limits the flexibility of the system with respect to the range of PCLK and CLKIN frequencies that can be effectively supported. System 100 also has disadvantages associated with its method for determining data sampling edges, as explained further below.
The gear ratio logic 114 also generates edge information that is used by data and control logic 116 to generate a control signal 126 that dictates which CLKIN edges are used by data and control logic 120 to sample data. Because CLKIN is faster than PCLK (usually CLKIN is approximately a multiple of PLCK) multiple CLKIN edges are available to sample data in a given PLCK cycle. One method for determining sampling edges is to assign color values to cycles in a clock period that is common to CLKIN and PCLK. Assuming phase alignment of PCLK and CLKIN signals and a defined reference starting point, the color values identify CLKIN edges upon which data transfers should take place. One disadvantage of this method is that the control signal 126 specifying sampling edges is generated and loaded every common clock cycle. Generating and loading the control signal anew each common clock cycle is a timing challenge. In addition, this method adds significant complexity to the verification and testing process. For example, test vectors must be written for all possible cases, and logic must be added to generate the vectors and the control signals.
There is therefore a need for a method and apparatus for synchronizing data transfer across a clock domain boundary with greater flexibility in the choice of clock frequencies. There is a further need for such a method and apparatus that is less expensive to implement, is more reliable, and is easier to test and verify.